1. Field of the Invention
The present invention is generally in the field of integrated circuits. More specifically, the invention is in the field of ESD protection for integrated circuits.
2. Related Art
In a mixed signal integrated circuit (IC), power connections to various circuit blocks within the IC are typically independent of each other to reduce noise coupling. Power that feeds a particular circuit block in the IC is referred to as a “power domain” in the present application. Signal lines are typically required to connect a circuit block with an independent power bus to another circuit block. Thus, under normal operating conditions, only signal lines connect a circuit block of one power domain to the circuit block of another power domain. However, unless the power domains are linked together, gate oxide of input logic in the circuit blocks can be ruptured by a large voltage drop that can occur between power domains in an electrostatic discharge (ESD) event.
In a conventional approach, back-to-back diodes are placed between the power buses of the various power domains to isolate the power domains during normal operation yet link the power domains together during an ESD event. However, during an ESD event, an ESD discharge path can cross many power domains and, thereby, cause multiple diode voltage drops across the back-to-back diodes that are situated between the power domains. The multiple diode voltage drops, along with voltage drops resulting from power bus resistance, can significantly damage gate oxide of circuit block input logic. Thus, the conventional approach of placing back-to-back diodes between power buses of the power domains in an IC does not provide effective gate oxide protection during an ESD event.
Thus, there is a need in the art for effective ESD protection for gate oxide in circuit blocks with independent power domains in an integrated circuit.